module clok_div_10hz(clk_1khz,clk_10hz,rst);
/*
 *实现100分频
 * Author: xianwu Liang
 */
    input clk_1khz;
    input rst;
	 output reg clk_10hz;
	 reg[5:0] cnt_10hz; 
	 
	 //1khz -> 10hz 100分频
	always @(posedge clk_1khz or negedge rst)
		 if(!rst) begin
			  cnt_10hz    <= 6'b000000;
			  clk_10hz    <= 1'b0;
		 end
		 else if(cnt_10hz < 6'b110000) begin
			  cnt_10hz <= cnt_10hz + 1'b1;
		 end
		 else begin
			  cnt_10hz <= 6'b000000;
			  clk_10hz <= ~clk_10hz;
		 end
		 
endmodule